Embodiments of the invention relate to a synchronization system and a frequency divider circuit that generates a divided clock used in the synchronization system.
FIG. 13 is a block diagram showing an example of the configuration of the conventional synchronization system 80. The synchronization system 80 shown in FIG. 13 includes a first device 82, a second device 84, a frequency divider circuit 88, and a decoder 92.
The first device 82 operates in synchronization with a reference clock (clk_PLL) supplied from a clock generation circuit, such as a phase locked loop (PLL) 93, and the second device 84 operates in synchronization with a divided clock generated by dividing the reference clock (clk_PLL) through the frequency divider circuit 88.
The division ratio of the divided clock can be changed by a first division ratio set by a division ratio setting signal (div_ratio) input from the outside.
Hereinafter, the frequency divider circuit 88 will be described.
FIG. 14 is a circuit diagram showing an example of the configuration of the frequency divider circuit 88 shown in FIG. 13. The frequency divider circuit 88 shown in FIG. 14 includes a selector 98, a flip-flop (FF) 100, a decrementer (−1) 102, and NOR circuit 104.
In the frequency divider circuit 88, when the output signal of the decrementer 102 becomes 0, the output signal of the NOR circuit 104 becomes a high level (H), and a first division ratio set by the division ratio setting signal (div_ratio [n:0]) is output from the selector 98. The first division ratio output from the selector 98 is set in the FF 100 in synchronization with a reference clock (clk_PLL), and a count value (count, downcount [n:0]) output from the FF 100 becomes the first division ratio.
Then, the count value output from the FF 100 is decremented (−1) by the decrementer 102. When the output signal of the decrementer 102 is not 0, the output signal of the decrementer 102 is output from the selector 98. The output signal from the selector 98 is set in the FF 100 in synchronization with the reference clock (clk_PLL), and the count value output from the FF 100 is counted down.
The count value is sequentially decremented, and is counted down from the first division ratio to 0 in synchronization with the reference clock (clk_PLL). Then, when the output signal of the decrementer 102 becomes 0, the first division ratio is set again to the count value, and the above-described operation is repeated. In the meantime, from the frequency divider circuit 88, the count value (count) of the FF 100 is output and the most significant bit (downcount [n]) is output as a divided clock (clk_DIV).
In the synchronization system 80, communication between the first device 82 and the second device 84 is performed through a bus 86 operating in synchronization with the divided clock. Typically, the divided clock itself is not input to the first device 82. Instead, strobe signals composed of an input strobe signal (strobe_sample) and an output strobe signal (strobe_drive) are input to the first device 82 from the decoder 92. These two strobe signals allow the first device 82 to normally communicate with the second device 84.
The input strobe signal is a signal for controlling the timing at which the first device 82 receives a signal input from the second device 84, whereas the output strobe signal is a signal for controlling the timing at which the first device 82 outputs a signal input to the second device 84.
As described above, the divided clock is generated by dividing the reference clock (clk_PLL). Accordingly, it is easiest to generate the input strobe signal and the output strobe signal by decoding the count value output from the frequency divider circuit 88. For this reason, the two strobe signals are generated by decoding the count value based on the first division ratio and the count value through the decoder 92.
In the synchronization system 80, as described above, the reference clock (clk_PLL) is divided by the frequency divider circuit 88 to generate the count value and the divided clock, the count value is decoded by the decoder 92 to generate the input strobe signal and the output strobe signal, and the first device 82 communicates with the second device 84 through the bus 86 based on the two strobe signals.
In the conventional synchronization system 80, however, there has been a problem in terms of timing closure.
FIG. 15 is a block diagram showing an example of the problem in the conventional synchronization system 80. As shown in FIG. 15, in the actual synchronization system 80, in order to reduce a clock skew between the first device 82 and the second device 84, clock tree synthesis (CTS) is usually performed in the paths of the reference clock (clk_PLL) and the divided clock, and a clock tree is inserted.
In this case, even if the phases of clocks between the first device 82 and the second device 84 coincide with each other, a clock skew between the count value output from the frequency divider circuit 88 and the reference clock (clk_PLL) input to the first device 82 is increased since the frequency divider circuit 88 is located near the root of the clock tree. Therefore, significant hold violation occurs between the frequency divider circuit 88 and the first device 82.
In addition, there is a disadvantage in terms of the number of pins when mounting the synchronization system 80. As shown by the dotted line in FIGS. 13 and 14, in a case where the frequency divider circuit 88 is mounted as a semiconductor chip different from other circuit portions, the division ratio setting signal and the count value output from the frequency divider circuit 88 need to be input to the decoder 92. Each of these signals is configured with multiple-bit, and accordingly, when the frequency divider circuit 88 is mounted as another semiconductor chip, a large number of pins are required.
Moreover, when changing the first division ratio set by the division ratio setting signal, it is necessary to change the first division ratio in synchronization with the reference clock (clk_PLL) in order to prevent a malfunction. Furthermore, if the cycle of the reference clock (clk_PLL) at which the first division ratio is changed is different in the frequency divider circuit 88 and the decoder 92, the synchronization system 80 malfunctions. Therefore, timing requirement for changing the first division ratio is very severe.
Here, as related prior art documents, JP 06-56954 B (Patent document 1) and JP 2008-28854 A (Patent document 2) are mentioned.
Patent document 1 describes that a synchronous clock is counted by a counting circuit, and in a case where the count values from 0 to 3 are repeatedly counted, a timing signal is generated when the count value becomes 3.
Patent document 2 describes that the number of pulse of a basic signal is counted during the time period corresponding to one period of the reference clock signal.